Renesas RL78/G1P Hardware User Manual page 729

RL78/G1P
Instruction Mnemonic
Group
8-bit CMP A, #byte
operation
!addr16, #byte
ES:!addr16, #byte
saddr, #byte
A, r
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
CMP0 A
X
B
C
!addr16
ES:!addr16
saddr
CMPS X, [HL+byte]
X, ES:[HL+byte]
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 26-5. Operation List (10/18)
Operands Bytes
Note 1
2
4
5
3
Note 3
2
2
3
4
2
1
2
2
3
2
3
2
3
1
1
1
1
3
4
2
3
4
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the program memory area is accessed.
CLK
Clocks
Note 2

1 A – byte
1 4 (addr16) – byte
2 5 (ES:addr16) – byte

1 (saddr) – byte

1 A – r

1 r – A
1 4 A – (addr16)
2 5 A – (ES:addr16)

1 A – (saddr)
1 4 A – (HL)
2 5 A – (ES:HL)
1 4 A – (HL+byte)
2 5 A – ((ES:HL)+byte)
1 4 A – (HL+B)
2 5 A – ((ES:HL)+B)
1 4 A – (HL+C)
2 5 A – ((ES:HL)+C)

1 A – 00H

1 X – 00H

1 B – 00H

1 C – 00H
1 4 (addr16) – 00H
2 5 (ES:addr16) – 00H

1 (saddr) – 00H
1 4 X – (HL+byte)
2 5 X – ((ES:HL)+byte)
CHAPTER 26 INSTRUCTION SET
Operation Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× 0 0
× 0 0
× 0 0
× 0 0
× 0 0
× 0 0
× 0 0
× × ×
× × ×
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