Renesas RL78/G1P Hardware User Manual page 673

RL78/G1P
20.8.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
IAWEN bit is used in invalid memory access detection function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-12. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H After reset: 00H
Symbol 7
IAWCTL IAWEN
Note
IAWEN
0
1
Note Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1.
Remark By specifying WDTON = 1 for the option byte (watchdog timer operation enable), the invalid memory
access function is enabled even IAWEN = 0.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
R/W
6 5
0 GRAM1
Disable the detection of invalid memory access.
Enable the detection of invalid memory access.
CHAPTER 20 SAFETY FUNCTIONS
4 3
GRAM0 0
Control of invalid memory access detection
2 1
GPORT GINT
0
GCSC
654