Renesas RL78/G1P Hardware User Manual page 574

RL78/G1P
Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol <7>
DMCn STGn
IFCn2 IFCn1
0
0
0
0
1
1
1
1
Other than above
Note The software trigger (STGn) can be used regardless of the IFCn2 to IFCn0 bits values.
Remark n: DMA channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 13-4. Format of DMA Mode Control Register n (DMCn) (2/2)
After reset: 00H
<6> <5>
DRSn DSn
IFCn0
0 0
0 1 INTAD
1 0 INTTM00
1 1 INTTM01
0 0 INTTM02
0 1 INTTM03
1 0 INTSR0/INTCSI01
1 1 INTST0
Setting prohibited
R/W
<4> 3
DWAITn 0
Selection of DMA start source
Trigger signal

CHAPTER 13 DMA CONTROLLER
2 1
IFCn2 IFCn1
Note
Trigger contents
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
A/D conversion end interrupt
End of timer channel 00 count or capture
end interrupt
End of timer channel 01 count or capture
end interrupt
End of timer channel 02 count or capture
end interrupt
End of timer channel 03 count or capture
end interrupt
UART0 transmission transfer end or
buffer empty interrupt/CSI00 transfer end
or buffer empty interrupt
UART0 reception transfer end interrupt
0
IFCn0
555