Renesas RL78/G1P Hardware User Manual page 575

RL78/G1P
13.3.2 DMA operation control register n (DRCn)
The DRCn register is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFFBCH (DRC0), FFFBDH (DRC1)
Symbol <7>
DRCn DENn
DENn
0
1
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn
0
1
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by the IFCn2 to IFCn0 bits is input, DMA transfer is
started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated without
waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set the DSTn bit to 0 and then
the DENn bit to 0 (for details, see 13.5.5 Forced termination by software).
Remark n: DMA channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 13-5. Format of DMA Operation Control Register n (DRCn)
After reset: 00H
6 5
0 0
Disables operation of DMA channel n (stops operating cock of DMA).
Enables operation of DMA channel n.
DMA transfer of DMA channel n is completed.
DMA transfer of DMA channel n is not completed (still under execution).
CHAPTER 13 DMA CONTROLLER
R/W
4 3
0 0
DMA operation enable flag
DMA transfer mode flag
2 1 <0>
0 0 DSTn
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