Renesas RL78/G1P Hardware User Manual page 152

RL78/G1P
Figure 6-2. Internal Block Diagram of Channel 0 of Timer Array Unit 0
CK00
CK01
Edge
Noise
TI00
detection
filter
TNFEN00
Noise filter
Channel 0
enable register 1
(NFEN1)
Interrupt signal to slave channel
Figure 6-3. Internal Block Diagram of Channel 1 of Timer Array Unit 0
Timer input select register 0
(TIS0)
TIS02 TIS01 TIS00
Interrupt signal from master channel
CK00
CK01
CK02
CK03
f
IL
Noise
filter
TI01
TNFEN01
Noise filter
enable register 1
(NFEN1)
Channel 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
f
MCK
Timer
f
TCLK
controller
Mode
selection
CKS001 CKS000 CCS00
0
f
f
TCLK
MCK
controller
selection
Edge
detection
SPLIT
CKS011 CKS010 CCS01
01
Output controller
Interrupt controller
Timer counter register 00 (TCR00)
Timer data register 00 (TDR00)
STS STS STS
CIS001 CIS000 MD003 MD002 MD001 MD000
002 001 000
Timer mode register 00 (TMR00)
Timer
Output controller
Mode
Interrupt controller
Timer counter register 01 (TCR01)
Timer data register 01 (TDR01)
8-bit timer
controller
Interrupt controller
Mode
selection
STS STS STS
CIS011 CIS010 MD013 MD012 MD011 MD010
012 011 010
Timer mode register 01 (TMR01)
CHAPTER 6 TIMER ARRAY UNIT
Output latch
(Pxx)
INTTM00 (Timer interrupt)
Timer status
register 00 (TSR00)
OVF00
Overflow
Output latch
(Pxx)
INTTM01 (Timer interrupt)
Timer status
register 01 (TSR01)
OVF01
Overflow
INTTM01H (Timer interrupt)
TO00
PMxx
TO01
PMxx
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