Renesas RL78/G1P Hardware User Manual page 420

16-bit single-chip microcontroller

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Transmit data is set

Sampling timing

While SSImn is at high level, transmission is not performed even if the falling edge of SCKmn (serial clock) arrives,

and neither is receive data sampled in synchronization with the rising edge.

When SSImn goes to low level, data is output (shifted) in synchronization with the falling edge of the serial clock

and a reception operation is performed in synchronization with the rising edge.

Transmit data is set

Sampling timing

If DAPmn = 1, when transmit data is set while SSImn is at high level, the first data (bit 7) is output to the

data output. However, no shift operation is performed even if the rising edge of SCKmn (serial clock)

arrives, and neither is receive data sampled in synchronization with the falling edge. When SSImn goes

to low level, data is output (shifted) in synchronization with the next rising edge and a reception operation

is performed in synchronization with the falling edge.

m: Unit number (m = 0), n: Channel number (n = 0)

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 11-76. Slave Select Input Function Timing Diagram

CHAPTER 11 SERIAL ARRAY UNIT