Renesas RL78/G1P Hardware User Manual page 585

RL78/G1P
13.5.5 Forced termination by software
After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn
bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn)
of DMAn, therefore, perform either of the following processes.
<When using one DMA channel>
 Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8-
bit manipulation instruction).
 Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the
DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
<When using two DMA channels>
 To forcibly terminate DMA transfer by software when using two or more DMA channels (by setting DSTn to 0), clear
the DSTn bit to 0 after the DMA transfer is held pending by setting the DWAITn bits of all using channels to 1. Next,
clear the DWAITn bits of all using channels to 0 to cancel the pending status, and then clear the DENn bit to 0.
Example 1
DSTn = 0
DSTn = 0?
DENn = 0
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 13-11. Forced Termination of DMA Transfer (1/2)
No
Yes
(f : CPU clock)
CLK CLK
CHAPTER 13 DMA CONTROLLER
Example 2
DSTn = 0
2 clock wait
DENn = 0
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