Renesas RL78/G1P Hardware User Manual page 654

RL78/G1P
19.4.3 When used as interrupt and reset mode
 When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V
V ) by using the option byte 000C1H.
LVDL
Start in the following initial setting state.
Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level

register (LVIS))
 When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
 Operation in LVD interrupt & reset mode
In the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0), the state of an internal reset by LVD is
retained until the supply voltage (V
The internal reset is released when the supply voltage (V
An interrupt request signal by LVD (INTLVI) is generated and arbitrary save processing is performed when the
supply voltage (V
generated when the supply voltage (V
generated, an interrupt request signal is not generated even if the supply voltage becomes equal to or higher than
the high-voltage detection voltage (V
To use the LVD reset & interrupt mode, perform the processing according to Figure 19-7 Processing
Procedure After an Interrupt Is Generated and Figure 19-8 Initial Setting of Interrupt and Reset Mode.
Figure 19-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) exceeds the high-voltage detection level (V
DD
) falls below the high-voltage detection level (V
DD
) falls below the low-voltage detection level (V
DD
) without falling below the low-voltage detection voltage (V
LVDH
CHAPTER 19 VOLTAGE DETECTOR
).
LVDH
) exceeds the high-voltage detection level (VLVDH).
DD
). After that, an internal reset by LVD is
LVDH
) after power is supplied.
LVDH
). After INTLVI is
LVDL
).
LVDL
,
LVDH
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