Renesas RL78/G1P Hardware User Manual page 217

RL78/G1P
Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets the corresponding bit of the noise filter enable
default register 1 (NFEN1) to 0 (off) or 1 (on).
setting
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation Sets the TSmn bit to 1.
start The TSmn bit automatically returns to 0 because it is a
trigger bit.
Detects the TImn pin input count start valid edge.
During Set value of the TDRmn register can be changed.
operation The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TMRmn register, TOMmn, TOLmn,
TOmn, and TOEmn bits cannot be changed.
Operation The TTmn bit is set to 1.
stop The TTmn bit automatically returns to 0 because it is a
trigger bit.
TAU The TAUmEN bit of the PER0 register is cleared to 0.
stop
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
Input clock supply for timer array unit 0 is stopped.
(Clock supply is stopped and writing to each register is
disabled.)
Input clock supply for timer array unit 0 is supplied. Each
channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and the TImn pin start edge detection wait
status is set.
Clears timer count register mn (TCRmn) to 0000H and
starts counting up.
When the TImn pin start edge is detected, the counter
(TCRmn) counts up from 0000H. If a capture edge of the
TImn pin is detected, the count value is transferred to
timer data register mn (TDRmn) and INTTMmn is
generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared. The TCRmn register stops
the count operation until the next TImn pin start edge is
detected.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
Input clock supply for timer array unit 0 is stopped.
All circuits are initialized and SFR of each channel is
also initialized.
198