Operation As Input Pulse Interval Measurement - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.8.3 Operation as input pulse interval measurement

The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In
addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit
is set to 1.
The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock  ((10000H  TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts
up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to
timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is
output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter
does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
capture trigger.
Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement
Operation clock
TNFENmn
Noise
TImn pin
filter
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CKm1
Note
CKm0
Edge
NFEN1
detection
register
TSmn
CHAPTER 6 TIMER ARRAY UNIT
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Interrupt
Interrupt signal
controller
(INTTMmn)
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