Renesas RL78/G1P Hardware User Manual page 458

16-bit single-chip microcontroller
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RL78/G1P
Starting setting for resumption
(Essential)
(Selective)
(Selective)
Changing setting of the SPSm register
(Selective)
Changing setting of the SDRmn register
(Selective)
Changing setting of the SMRmn register
(Selective)
Changing setting of the SCRmn register
(Selective)
Changing setting of the SOLm register
(Selective)
Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Essential)
Changing setting of the SOEm register
(Essential)
(Essential)
Writing to the SSm register
Completing resumption
Remark
If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the
transmission target stops or transmission finishes, and then perform initialization instead of restarting the
transmission.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-103. Procedure for Resuming UART Transmission
No
Completing master
preparations?
Yes
Port manipulation
Port manipulation
setting
CHAPTER 11 SERIAL ARRAY UNIT
Wait until stop the communication target or
communication operation completed
Disable data output of the target channel by setting
a port mode register.
Re-set the register to change the operation clock
setting.
Re-set the register to change the transfer baud
rate setting (setting the transfer clock by dividing
the operation clock (f
)).
MCK
Re-set the register to change serial mode register
mn (SMRmn) setting.
Re-set the register to change the serial
communication operation setting register mn
(SCRmn) setting.
Re-set the register to change serial output level
register m (SOLm) setting.
Clear the SOEmn bit to 0 and stop output.
Set the initial output level of the serial data
(SOmn).
Set the SOEmn bit to 1 and enable output.
Enable data output of the target channel by setting
a port register and a port mode register.
Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
Setting is completed.
Set transmit data to the SDRmn [7:0] bits (TXDq
register) (8 bits) or the SDRmn [8:0] bits (9 bits)
and start communication.
439

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