Renesas RL78/G1P Hardware User Manual page 484

RL78/G1P
Filter
SDAA0/
SDAA1/
P61 Noise
eliminator
DFC0
N-ch open-
drain output
Output
PM61
latch
( P61)
Filter
SCLA0/
SCLA1/
P60
Noise
eliminator
DFC0
N-ch open-
drain output
Output
PM60
latch
( P60)
Caution The RL78/G1P can wait simultaneously because they have channels 0 and 1. However, they cannot
communicate simultaneously as they share the P60/SCLA0/SCLA1 and P61/SDAA0/SDAA1 pins.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-1. Block Diagram of Serial Interface IICA0, IICA1
WUP0
Controller for
STOP mode
Slave address
register 0 (SVA0)
Match
signal
IICA shift
register 0 (IICA0)
TRC0
Output control
ACK detector
Start condition
detector
Stop condition
detector
Serial clock
counter
Serial clock
controller
f
CLK
Counter
f /2
CLK
Match signal
IICCTL01.PRS0
IICA low-level width IICA high-level width
setting register 0 (IICWH0)
setting register 0 (IICWL0)
Controller for
STOP mode
IICA shift register 1
(IICA1)
Output control
Serial clock
counter
Serial clock
controller
CHAPTER 12 SERIAL INTERFACE IICA
Internal bus
MSTS 0 ALD0 EXC0 COI0 TRC0 ACKD 0 STD0 SPD0
IICA control register 00
(IICCTL00)
IICE0 LREL 0 WREL 0SPIE0 WTIM 0 ACKE 0 STT0 SPT0
Clear
condition
Set generator
SO latch
condition
D Q
generator
IICWL0
Data hold
time correction
circuit
ACK
generator
Interrupt request
signal generator
Serial clock
wait controller
IICA shift register 0 (IICA0)
IICCTL00.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
WUP0 CLD0 DAD0
IICA control register 01
(IICCTL01)
Internal bus
IICA status register 0
(IICS0)
Start
Stop
Wakeup
controller
INTIICA0
IICS0.MSTS0, EXC0, COI0
Bus status
detector
SMC0 DFC0 PRS0 STCF0 IICBSY0 STCEN0 IICRSV0
IICA flag register 0
(IICF0)
Channel 0
Channel 1
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