Renesas RL78/G1P Hardware User Manual page 339

16-bit single-chip microcontroller
Hide thumbs Also See for RL78/G1P:
Table of Contents

Advertisement

RL78/G1P
Figure 11-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01)
Symbol
15
14
SCRmn
TXE
RXE
mn
mn
TXE
RXE
mn
mn
0
0
0
1
1
0
1
1
DAP
CKP
mn
mn
0
0
0
1
1
0
1
1
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode.
EOC
mn
0
Disables generation of error interrupt INTSREx (INTSRx is generated).
1
Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
Set EOCmn = 0 in the CSI mode and during UART transmission
Notes 1. The SCR00 register only.
2. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated.
Caution Be sure to clear bits 3, 6, and 11 to "0" (Also clear bit 5 of the SCR01 register to 0). Be sure to set bit
2 to "1".
Remark
m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
13
12
11
10
DAP
CKP
0
EOC
mn
mn
mn
Disable communication.
Reception only
Transmission only
Transmission/reception
Selection of data and clock phase in CSI mode
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
Mask control of error interrupt signal (INTSREx (x = 0))
CHAPTER 11 SERIAL ARRAY UNIT
After reset: 0087H
9
8
7
6
PTC
PTC
DIR
0
mn1
mn0
mn
n1
Setting of operation mode of channel n
D7 D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
Note 2
.
R/W
5
4
3
2
SLCm
SLC
0
1
Note 1
mn0
D1
D0
D1
D0
D1
D0
D1
D0
1
0
DLSm
DLS
n1
mn0
Type
1
2
3
4
320

Advertisement

Table of Contents
loading

Table of Contents