Renesas RL78/G1P Hardware User Manual page 463

16-bit single-chip microcontroller

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11.7.2 UART reception

UART reception is an operation wherein the RL78/G1P asynchronously receives data from another device (start-stop

synchronization).

For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both

the odd- and even-numbered channels must be set.

Target channel

Error interrupt

Error detection flag

Transfer data length

Transfer rate

Data direction

Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics

in the electrical specifications (see CHAPTER 27 ELECTRICAL SPECIFICATIONS).

Remarks 1. f

: Operation clock frequency of target channel

: System clock frequency

2. m: Unit number (m = 0), n: Channel number (n = 1), mn = 01

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Channel 1 of SAU0

Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)

 Framing error detection flag (FEFmn)

 Parity error detection flag (PEFmn)

 Overrun error detection flag (OVFmn)

7, 8 or 9 bits

/6 [bps] (SDRmn [15:9] = 2 or more), Min. f

Non-reverse output (default: high level)

Reverse output (default: low level)

The following selectable

 No parity bit (no parity check)

 No parity judgment (0 parity)

 Even parity check

 Odd parity check

MSB or LSB first

CHAPTER 11 SERIAL ARRAY UNIT

 128) [bps]