Peripheral Enable Register 0 (Per0) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.3.1 Peripheral enable register 0 (PER0)

The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a
hardware that is not in use is stopped in order to reduce power consumption and noise.
When the A/D converter is to be used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F0H After reset: 00H
Symbol 7
PER0 0
ADCEN
0
1
Cautions 1. When setting the A/D converter, be sure to set the following registers first while the ADCEN
bit is set to 1. If ADCEN = 0, the values of the A/D converter control registers are cleared to
their initial values and writing to them is ignored (except for port mode registers 0, 2, 12 and
14 (PM0, PM2, PM12, PM14), port mode control registers 0, 12, and 14 (PMC0, PMC12, PMC14),
and A/D port configuration register (ADPC)).
 A/D converter mode register 0 (ADM0)
 A/D converter mode register 1 (ADM1)
 A/D converter mode register 2 (ADM2)
 12-bit A/D conversion result register (ADCR)
 8-bit A/D conversion result register (ADCRH)
 Analog input channel specification register (ADS)
 Conversion result comparison upper limit setting register (ADUL)
 Conversion result comparison lower limit setting register (ADLL)
 A/D test register (ADTES)
2. Be sure to clear bits 1, 3, and 7 to "0".
Note 24-pin products only
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-2. Format of Peripheral Enable Register 0 (PER0)
R/W
<6> <5>
IICA1EN ADCEN
Stops input clock supply.
 SFR used by the A/D converter cannot be written.
 The A/D converter is in the reset status.
Enables input clock supply.
 SFR used by the A/D converter can be read/written.
<4> 3
IICA0EN 0
Control of A/D converter input clock supply
CHAPTER 9 A/D CONVERTER
<2> 1
SAU0EN 0
<0>
TAU0EN
247