Renesas RL78/G1P Hardware User Manual page 460

RL78/G1P
Figure 11-105. Flowchart of UART Transmission (in Single-Transmission Mode)
Writing transmit data to the SDRmn
[7:0] bits (TXDq register) (8 bits) or
the SDRmn [8:0] bits (9 bits)
Wait for transmit completes
Writing transmit data to the SDRmn
[7:0] bits (TXDq register) (8 bits) or
the SDRmn [8:0] bits (9 bits)
No
Transmission completed?
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Starting UART
communication
SAU default setting
Setting transmit data
Enables interrupt
Transfer end interrupt
Transmitting next data?
Yes
RETI
Yes
Disable interrupt (MASK)
Write STmn bit to 1
End of communication
CHAPTER 11 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 11-101.
(Select transfer end interrupt)
Set data for transmission and the number of data. Clear
communication end flag (Storage area, transmission data pointer,
number of communication data and communication end flag are
optionally set on the internal RAM by the software).
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and setinterrupt enable (EI).
Read transmit data from storage area and write it to TxDq. Update transmit
data pointer.
Communication starts by writing to SDRmn[7:0].
When Transfer end interrupt is
generated, it moves to interrupt
processing routine.
No
Read transmit data, if any, from storage area
and write it to SIOp. Update transmit data
pointer.
If not, set transmit end flag.
Sets communication
completion flag
Check completion of transmission by
verifying transmit end flag.
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