Renesas RL78/G1P Hardware User Manual page 560

RL78/G1P
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Notes 1. Make sure that the time between the rise of the SCLAn pin signal and the generation of the start
condition after a restart condition has been issued is at least 4.7
at least 0.6
2. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-32. Example of Master to Slave Communication
H
H
H
L
L
H
ACK
D 3 D 2 D 1 D 0
1 1 1 1
<7>
L
H
H
L
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices

s when specifying fast mode.
CHAPTER 12 SERIAL INTERFACE IICA
<iii>
<ii>
<8>
Note 1
<i> Note 2
Restart condition
AD5 AD4 AD3 AD2
AD6
Slave address

s when specifying standard mode and
AD1
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