Renesas RL78/G1P Hardware User Manual page 215

RL78/G1P
Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Operation clock
TNFENmn
Noise
TImn pin
filter
Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 6-54. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TCRmn
TDRmn
INTTMmn
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 3)
2. TSmn:
TEmn:
TImn:
TCRmn:
TDRmn:
OVF:
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CKm1
Note
CKm0
NFEN1
Edge
register
detection
TSmn
TEmn
TImn
FFFFH
0000H
0000H
OVF
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
TImn pin input signal
Timer count register mn (TCRmn)
Timer data register mn (TDRmn)
Bit 0 of timer status register mn (TSRmn)
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
a
a
CHAPTER 6 TIMER ARRAY UNIT
Interrupt
controller
b
c
b c
Interrupt signal
(INTTMmn)
196