Renesas RL78/G1P Hardware User Manual page 501

RL78/G1P
12.3.6 IICA low-level width setting register n (IICWLn)
This register is used to set the low-level width (t
data hold time is decided by value the higher 6 bits of IICWL register.
The IICWLn register can be set by an 8-bit memory manipulation instruction.
Set the IICWLn register while operation of I
Reset signal generation sets this register to FFH.
For details about setting the IICWLn register, see 12.4.2 Setting transfer clock by using IICWLn and IICWHn
registers.
The data hold time is one-quarter of the time set by the IICWLn register.
Figure 12-10. Format of IICA Low-Level Width Setting Register n (IICWLn)
Address: F0232H (IICWL0), F023AH (IICWL1)
12.3.7 IICA high-level width setting register n (IICWHn)
This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA.
The IICWHn register can be set by an 8-bit memory manipulation instruction.
Set the IICWHn register while operation of I
Reset signal generation sets this register to FFH.
Figure 12-11. Format of IICA High-Level Width Setting Register n (IICWHn)
Address: F0233H (IICWH0), F023BH (IICWH1)
Remarks 1. For how to set the transfer clock by using the IICWLn and IICWHn registers, see 12.4.2 Setting transfer
clock by using IICWLn and IICWHn registers.
2. n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
LOW
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
Symbol 7 6
IICWLn
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
Symbol 7 6
IICWHn
CHAPTER 12 SERIAL INTERFACE IICA
) of the SCLAn pin signal that is output by serial interface IICA. The
After reset: FFH R/W
5 4 3 2
After reset: FFH R/W
5 4 3 2
1 0
1 0
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