Renesas RL78/G1P Hardware User Manual page 598

RL78/G1P
15.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, and IF1L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L and
IF0H registers are combined to form 16-bit register IF0, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 15-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
Address: FFFE0H After reset: 00H R/W
Symbol <7>
IF0L PIF5
Address: FFFE1H
Symbol <7>
IF0H SREIF0
TMIF01H
Address: FFFE2H
Symbol <7>
IF1L TMIF03
XXIFX
0
1
Cautions 1. Be sure to set bits that are not available to the initial value.
2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
"IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
"IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at
"mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
<6> <5>
PIF4 PIF3
After reset: 00H R/W
<6> <5>
SRIF0 STIF0
CSIIF00
After reset: 00H R/W
<6> <5>
TMIF02 TMIF01
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
CHAPTER 15 INTERRUPT FUNCTIONS
<4> <3>
PIF2 PIF1
<4> <3>
DMAIF1 DMAIF0
<4> <3>
TMIF00 IICAIF1 TMIF03H
Interrupt request flag
<2> <1> <0>
PIF0 LVIIF WDTIIF
<2> <1> <0>
FLIF IICAIF0 ADIF
<2> 1
0
0
0
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