Renesas RL78/G1P Hardware User Manual page 479

RL78/G1P
SMRmn
Register
CKSmn PRS PRS
m13 m12
0 X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note When changing the clock selected for f
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU).
Remarks 1. X: Don't care
2. m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 11-5. Selection of Operation Clock for UART
SPSm Register
PRS PRS PRS PRS
m11 m10 m03 m02
X X X 0 0
X X X 0 0
X X X 0 0
X X X 0 0
X X X 0 1
X X X 0 1
X X X 0 1
X X X 0 1
X X X 1 0
X X X 1 0
X X X 1 0
X X X 1 0
X X X 1 1
X X X 1 1
X X X 1 1
X X X 1 1
0 0 0 X X
0 0 1 X X
0 1 0 X X
0 1 1 X X
1 0 0 X X
1 0 1 X X
1 1 0 X X
1 1 1 X X
0 0 0 X X
0 0 1 X X
0 1 0 X X
0 1 1 X X
1 0 0 X X
1 0 1 X X
1 1 0 X X
1 1 1 X X
Other than above
CHAPTER 11 SERIAL ARRAY UNIT
Operation Clock (f
PRS PRS
m01 m00
0 0 f
CLK
0 1 f /2
CLK
2
1 0 f /2
CLK
3
1 1 f /2
CLK
4
0 0 f /2
CLK
5
0 1 f /2
CLK
6
1 0 f /2
CLK
7
1 1 f /2
CLK
8
0 0 f /2
CLK
9
0 1 f /2
CLK
10
1 0 f /2
CLK
11
1 1 f /2
CLK
12
0 0 f /2
CLK
13
0 1 f /2
CLK
14
1 0 f /2
CLK
15
1 1 f /2
CLK
X X f
CLK
X X f /2
CLK
2
X X f /2
CLK
3
X X f /2
CLK
4
X X f /2
CLK
5
X X f /2
CLK
6
X X f /2
CLK
7
X X f /2
CLK
8
X X f /2
CLK
9
X X f /2
CLK
10
X X f /2
CLK
11
X X f /2
CLK
12
X X f /2
CLK
13
X X f /2
CLK
14
X X f /2
CLK
15
X X f /2
CLK
Setting prohibited
(by changing the system clock control register (CKC) value), do
CLK
Note
)
MCK
f = 32 MHz
CLK
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.63 kHz
7.81 kHz
3.91 kHz
1.95 kHz
977 Hz
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.63 kHz
7.81 kHz
3.91 kHz
1.95 kHz
977 Hz
460