Renesas RL78/G1P Hardware User Manual page 273

RL78/G1P
(4) A/D conversion times for 8-bit A/D conversion when there is power supply stabilization wait time
(for hardware trigger wait mode (except for the second and subsequent conversions
in sequential conversion mode and conversion of the channels specified for scan 1, 2, and 3 in scan mode
A/D Converter Mode Mode
Register 0 (ADM0)
FR2 FR1 FR0 LV0
0 0 0 0 Normal
1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 1 Normal
2
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power
supply do not occur after a hardware trigger is detected (see Table 9-3 (3/4)).
2. When using ANI16, setting this value is prohibited.
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 27.6.1 A/D converter characteristics.
Note that the conversion time (t
2. Rewrite the FR2 to FR0 and LV0 bits to other than the same data while conversion is stopped (ADCS =
0, ADCE = 0).
3. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
(Cautions 4 and Remark are listed on the next page.)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 9-3. A/D Conversion Time Selection (4/4)
Conversion Number of Number of
Clock (f ) A/D Power Conversion
AD
Supply
Stabilization (Number of
Sampling
Wait Clock
f /32 4 f 41 f
CLK CLK
(number of
sampling
f /16
CLK
clock:
11 f
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1 2 f
CLK CLK
f /32 58 f 53 f
CLK CLK
(number of
sampling
f /16
CLK
clock:
f /8
23 f
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1 29 f
CLK CLK
) does not include the A/D power supply stabilization wait time.
CONV
A/D Power Selected A/D Power Supply Stabilization Wait Times
Supply
Clock Stabilization
Wait Time +
f
Conversion
CLK
MHz
Clock) Time
1316/f Setting
AD CLK
prohibited
660/f
CLK
)
AD
332/f
CLK
250/f
CLK
209/f
CLK
168/f
CLK
86/f
CLK

43/f
43 s
CLK
Note 2
1754/f Setting
AD CLK
prohibited
906/f
CLK
482/f
)
CLK
AD
376/f
CLK
323/f
CLK
270/f
CLK
164/f
CLK

82/f
82 s
CLK
Note 2
CHAPTER 9 A/D CONVERTER
+ Conversion Times
V = 2.7 to 3.6 V
DD
= 1 f = 4 f = 8 f
CLK CLK CLK
MHz MHz
Setting Setting Setting
prohibited prohibited prohibited
41.25
Note 2

41.5 s 20.75
Note 2 Note 2

31.25 s 15.625
Note 2 Note 2

26.125 s 13.0625
Note 2 Note 2
 
42 s 21 s 10.5
Note 2 Note 2 Note 2
 
21.5 s 10.75 s 5.375
Note 2 Note 2 Note 2
 
10.75 s 5.375 s 2.6875
Note 2 Note 2 Note 2
Setting Setting Setting
prohibited prohibited prohibited
56.625

60.25 s 30.125
Note 2

47 s 23.5
Note 2

40.375 s 20.1875
Note 2
 
67.5 s 33.75 s 16.875
Note 2 Note 2
 
41 s 20.5 s 10.25
Note 2 Note 2
 
20.5 s 10.25 s 5.125
Note 2 Note 2
Note 1
))
= 16 f = 32
CLK
MHz MHz

41.125 s
Note 2
 
s 20.625 s
Note 2
 
s 10.375 s
Note 2
 
s 7.8125 s
Note 2
 
s 6.53125 s
Note 2
 
s 5.25 s
Note 2
 
s 2.6875 s
Note 2

Setting
s
prohibited

54.8125 s
 
s 28.3125 s
 
s 15.0625 s
 
s 11.75 s
 
s 10.09375 s
 
s 8.4375 s
 
s 5.125 s

s Setting
prohibited
)
CONV
254