Configuration Of Watchdog Timer - Renesas RL78/G1P Hardware User Manual

RL78/G1P

8.2 Configuration of Watchdog Timer

The watchdog timer includes the following hardware.
Counter
Control register
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Watchdog timer interval interrupt
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
Remark For the option byte, see CHAPTER 22 OPTION BYTE.
WDTINT of option
byte (000C0H)
WDCS2 to WDCS0 of
option byte (000C0H)
Clock
f
input
IL
controller
WINDOW1 and
WINDOW0 of option
byte (000C0H)
WDTON of option
byte (000C0H)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 8-1. Configuration of Watchdog Timer
Item
Internal counter (17 bits)
Watchdog timer enable register (WDTE)
Table 8-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Figure 8-1. Block Diagram of Watchdog Timer
Interval time controller
(Count value overflow time
6
f /2 to f
IL IL
17-bit
counter
Count clear
signal
Window size check
Watchdog timer enable
register (WDTE)
Internal bus
Configuration
Option Byte (000C0H)
Bit 7 (WDTINT)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
Bit 0 (WDSTBYON)

3/4 + 1/2 f )
IL
11
/2
Overflow signal
Selector
Window size
decision signal
Write detector to
WDTE except ACH
CHAPTER 8 WATCHDOG TIMER
Interval time interrupt
Reset
Internal reset signal
output
controller
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