Renesas RL78/G1P Hardware User Manual page 641

RL78/G1P
Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
(2) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0)
Supply voltage (V
DD
V
LVDH
V
LVDL
Lower limit voltage for guaranteed operation
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
0 V
High-speed on-chip
oscillator clock (f
High-speedsystem
clock (f
MX
(when X1 oscillation
is selected)
CPU operation stops
Internal reset signal
INTLVI
Notes 1. The high-speed on-chip oscillator clock and a high-speed system clock can be selected as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
3. After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage
detection level register (LVIS) are automatically set to 1. If the operating voltage returns to 2.7 V or higher
without falling below the voltage detection level (V
backup processing, and then use software to specify the initial settings in order (see Figure 19-8 Initial
Setting of Interrupt and Reset Mode).
4. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
the V (1.51 V, typ.) is reached.
POR
LVD reset processing time: 0 ms to 0.0701 ms (max.)
Remark V , V
LVDH LVDL
V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
and Voltage Detector (2/3)
)
Wait for oscillation
Note 2
accuracy stabilization
)
IH
Starting oscillation is specified by software
)
Normal operation (high-speed
on-chip oscillator clock)
LVD reset processing time
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
) is reached as well as the voltage stabilization wait + POR reset processing time after
LVDH
: LVD detection voltage
CHAPTER 18 POWER-ON-RESET CIRCUIT
Note 3
Reset period
(oscillation stop)
Note 1
Note 4
), after INTLVI is generated, perform the required
LVDL
Wait for oscillation
Note 2
accuracy stabilization
Starting oscillation is specified by software
Normal operation
(high-speed on-chip oscillator
Note 1
clock)
Operation stops
Note 4
LVD reset processing time
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
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