Setting Up Hardware Trigger No-Wait Mode - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.7.2 Setting up hardware trigger no-wait mode

Start of setup
PER0 register setting
ADPC and PMC1 register settings
PM register setting
 ADM0 register setting
 ADM1 register setting
 ADM2 register setting
 ADUL/ADLL register setting
 ADS register setting
(The order of the settings is
irrelevant.)
Reference voltage stabilization
wait time count A
ADCE bit setting
Reference voltage stabilization
wait time count B
ADCS bit setting
Hardware trigger standby status
Start of A/D conversion by
generating a hardware trigger
End of A/D conversion
Storage of conversion results in
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-30. Setting up Hardware Trigger No-Wait Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI7 pins: Set using the ADPC register
ANI16 pin: Set using the PMC1 register
The ports are set to the input mode.
 ADM0 register
FR2 to FR0, and LV0 bits:
ADMD bit: Select mode/scan mode
 ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait
ADSCM bit: Sequential conversion mode/one-shot conversion mode
 ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
ADRCK bit: This is used to select the range for the A/D conversion result comparison
ADTYP bit: 8-bit/12-bit resolution
 ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
 ADS register
ADS4, ADS2 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time count A is required when the value of the
ADREFP1 and ADREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 1, 0:
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: A = 1
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
If a high-accuracy channel is selected as the analog input channel: B = 0.5
If a standard channel is selected as the analog input channel: B = 2
After counting up to the reference voltage stabilization wait time count B ends, the ADCS
bit of the ADM0 register is set (1), and the system enters the hardware trigger standby
The A/D conversion operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
These are used to specify the A/D conversion time.
mode.
value generated by the interrupt signal from AREA1, AREA3, and AREA2.
CHAPTER 9 A/D CONVERTER
voltage source.
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A = 10 s
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s
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s
Note
s
285