Operation In Real-Time Output Mode - Renesas RL78/G1P Hardware User Manual

RL78/G1P

10.4.2 Operation in real-time output mode

D/A conversion is performed on each channel using the individual interrupt request signals from the ELC as triggers.
The setting method is described below.
<1> Set the DACEN bit of the PER1 register (peripheral enable register 1) to 1 to start the supply of the input
clock to the D/A converter.
<2> Use the ADPC register (port configuration register) to set the ports to analog pins.
<3> Set the DAMDi bit of the DAM register (D/A converter mode register) to 0 (normal mode).
<4> Set the analog voltage value to be output to the ANOi pin to the DACSi register (D/A conversion value setting
register i ).
<5> Set the DACEi bit of the DAM register to 1 (D/A conversion enable).
D/A conversion starts, and then, after the settling time elapses, the analog voltage set in step <3> is output to
the ANOi pin.
<6> Use the ELSELR register (ELC control register) to set the real-time trigger signal.
<7> Set the DAMDi bit of the DAM register to 1 (real-time output mode).
<8> Start the operation of the ECL request source.
Steps <1> to <8> above constitute the initial settings.
<9> Generation of the real-time output triggers starts D/A conversion and the analog voltage set in step <4> will
be output to the ANOi pin after a settling time has elapsed.
Set the analog voltage value to be output to the ANOi pin, to the DACSi register before performing the next
D/A conversion (real-time output trigger is generated).
Set the analog voltage value to be output to the ANOi pin, to the DACSi register before performing the next D/A
conversion (ELC trigger signal is generated).
When the DACEi bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops.
If the ports are set to digital pins by using the ADPC register, the ANOi pin goes into a high-impedance state when the
PM2i bit of the PM2 register for the port = 1 (input mode), and the ANOi pin outputs the set value of the
PM2 register when the PM2i bit = 0 (output mode).
Cautions 1. Even if 1, 0, and then 1 is set to the DACEi bit, there is a wait after 1 is set for the last time.
2. Make the interval between each generation of the ELC event request trigger signal longer than
the settling time. If an ELC event request trigger signal is generated during the settling time, D/A
conversion is aborted and reconversion starts.
3. Even if the generation of the ELC event request trigger signal and rewriting of the DACSi register
conflict, the D/A conversion result is output.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 10 D/A CONVERTER
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