Renesas RL78/G1P Hardware User Manual page 570

16-bit single-chip microcontroller

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13.2.2 DMA RAM address register n (DRAn)

This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n.

Addresses of the internal RAM area other than the general-purpose registers (see Table 13-2) can be set to this

Set the lower 16 bits of the RAM address.

This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8-bit

transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register.

When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in

the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.

In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.

The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.

Reset signal generation clears this register to 0000H.

Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1)

Table 13-2. Internal RAM Area Other than the General-purpose Registers

n: DMA channel number (n = 0, 1)

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 13-2. Format of DMA RAM Address Register n (DRAn)

DRA0H: FFFB3H

DRA1H: FFFB5H

CHAPTER 13 DMA CONTROLLER

After reset: 0000H

Internal RAM Area Other than the General-purpose Registers

FF900H to FFEDFH

DRA0L: FFFB2H

DRA1L: FFFB4H