Renesas RL78/G1P Hardware User Manual page 184

RL78/G1P
(2) Operation of event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the
TImn input.
f
MCK
TSmn (write)
TEmn
TImn input
Count clock
Start trigger
detection signal
TCRmn
TDRmn
Remark The above figure shows the timing when the noise filter is not in use. By making the noise filter on-state,
the edge detection becomes 2 f
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input
and that of the count clock (f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-26. Operation Timing (In Event Counter Mode)
<1>
<2>
Edge detection
<3>
<1>
Initial
m
value
<3>
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
MCK
).
MCK
CHAPTER 6 TIMER ARRAY UNIT
<4>
m1
m
Edge detection
m2
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