Configuration Of Timer Array Unit - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.2 Configuration of Timer Array Unit

Timer array unit includes the following hardware.
Item
Timer/counter
Register
Timer input
Timer output
Control registers
Note The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. For details,
see 4.5 Settings of Port Related Register When Using Alternate Function.
m: Unit number (m = 0), n: Channel number (n = 0 to 3)
Remark
Figure 6-1 to Figure 6-5 show the block diagrams of the timer array unit.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 6-1. Configuration of Timer Array Unit
Timer count register mn (TCRmn)
Timer data register mn (TDRmn)
TI00 to TI03
TO00 to TO03, output controller
<Registers of unit setting block>
 Peripheral enable register 0 (PER0)
 Timer clock select register m (TPSm)
 Timer channel enable status register m (TEm)
 Timer channel start register m (TSm)
 Timer channel stop register m (TTm)
 Timer input select register 0 (TIS0)
 Timer output enable register m (TOEm)
 Timer output register m (TOm)
 Timer output level register m (TOLm)
 Timer output mode register m (TOMm)
<Registers of each channel>
 Timer mode register mn (TMRmn)
 Timer status register mn (TSRmn)
 Noise filter enable register 1 (NFEN1)
 Port mode register (PMxx)
Note
 Port register (Pxx)
Note
CHAPTER 6 TIMER ARRAY UNIT
Configuration
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