Renesas RL78/G1P Hardware User Manual page 640

RL78/G1P
Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
(1) When the externally input reset signal on the RESET
Supply voltage (V
DD
Lower limit voltage for guaranteed operation
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
0 V
RESET pin
High-speed on-chip
oscillator clock (f )
IH
High-speedsystem
clock (f
MX
(when X1 oscillation
is selected)
CPU operation stops
Internal reset signal
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock can be selected as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
3. The time until normal operation starts includes the following reset processing time when the external reset
is released (release from the first external reset following release from the POR state) after the RESET
signal is driven high (1) as well as the voltage stabilization wait time after V
With the LVD circuit in use: 0.672 ms (typ.), 0.832 ms (max.)
With the LVD circuit not in use: 0.399 ms (typ.), 0.519 ms (max.)
4. The reset processing times in the case of the second or subsequent external reset following release from
the POR state are listed below.
With the LVD circuit in use: 0.531 ms (typ.), 0.675 ms (max.)
With the LVD circuit not in use: 0.259 ms (typ.), 0.362 ms (max.)
5. After power is supplied, the reset state must be retained until the operating voltage becomes in the range
defined in 27.4 AC Characteristics. This is done by controlling the externally input reset signal. After
power supply is turned off, this LSI should be placed in the STOP mode, or in the reset state by utilizing the
voltage detection circuit or externally input reset signal, before the voltage falls below the operating range.
When restarting the operation, make sure that the operation voltage has returned within the range of
operation.
Caution For power-on reset, be sure to use the externally input reset signal on the RESET
is off. For details, see CHAPTER 19 VOLTAGE DETECTOR.
Remark V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
and Voltage Detector (1/3)
)
Note 5
At least 10 µs
Wait for oscillation
Note 1
accuracy stabilization
Starting oscillation
is specified
by software
)
Reset processing time
when external reset
Note 3
is released.
Voltage stabilization wait
0.99 ms (TYP.), 2.30 ms (MAX.)
CHAPTER 18 POWER-ON-RESET CIRCUIT
____________
pin is used
Normal operation (high-speed
Note 2
on-chip oscillator clock)
Wait for oscillation
Note 1
accuracy stabilization
Starting oscillation
is specified by software
Reset
Normal operation
period
(high-speed on-chip
(oscillation
stop) oscillator clock)
Reset processing time when
Note 4
external reset is released.
(1.51 V, typ.) is reached.
POR
____________
pin when the LVD
Note 5
Note 2
Operation stops
____________
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