Renesas RL78/G1P Hardware User Manual page 580

RL78/G1P
13.5.2 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
 Consecutive capturing of A/D conversion results.
 DMA channel 1 is used for DMA transfer.
 DMA start source: INTAD
 Interrupt of A/D is specified by IFC12 to IFC10 = 0001B.
 Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register (ADCR) to 512 bytes of
FFCE0H to FFEDFH of RAM.
Remark IFC12 to IFC10: Bits 2 to 0 of DMA mode control registers 1 (DMC1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 13 DMA CONTROLLER
561