Renesas RL78/G1P Hardware User Manual page 153

RL78/G1P
Figure 6-4. Internal Block Diagram of Channel 2 of Timer Array Unit 0
Interrupt signal from master channel
CK00
CK01
Edge
Noise
TI02
detection
filter
TNFEN02
Noise filter
enable register 1
(NFEN1)
Channel 2
Interrupt signal to slave channel
Figure 6-5. Internal Block Diagram of Channel 3 of Timer Array Unit 0
Interrupt signal from master channel
CK00
CK01
CK02
CK03
Edge
Noise
TI03
filter detection
TNFEN03
Noise filter
enable register 1
(NFEN1)
Channel 3
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
f
MCK
f
controller
TCLK
selection
Slave/master
controller
CKS020 CCS02 MAS
CKS021
TER02
Timer
f
f
TCLK
MCK
controller
Mode
selection
CKS030 CCS31 SPLIT
CKS031
03
Timer
Output controller
Mode
Interrupt controller
Timer counter register 02 (TCR02)
Timer data register 02 (TDR02)
STS STS STS
CIS021 CIS020 MD023 MD022 MD021 MD020
022 021 020
Timer mode register 02 (TMR02)
Output controller
Interrupt controller
Timer counter register 03 (TCR03)
Timer data register 03 (TDR03)
8-bit timer
controller
Interrupt controller
Mode selection
STS STS STS
CIS031 CIS030 MD033 MD032 MD031 MD030
032 031 030
Timer mode register 03 (TMR03)
CHAPTER 6 TIMER ARRAY UNIT
Output latch
(Pxx)
INTTM02 (Timer interrupt)
Timer status
register 02 (TSR02)
OVF02
Overflow
Output latch
(Pxx)
INTTM03 (Timer interrupt)
Timer status
register 03 (TSR03)
OVF03
Overflow
INTTM03H (Timer interrupt)
TO02
PMxx
TO03
PMxx
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