Renesas RL78/G1P Hardware User Manual page 45

RL78/G1P
Data memory
space
Program
memory
space
Notes 1. Do not allocate the stack area, data buffers for use by the flash library, arguments of library functions,
branch destinations in the processing of vectored interrupts, or destinations or sources for DTC transfer to
the area from FFE20H to FFEDFH when performing self-programming or rewriting of the data flash memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. The flash libraries use the parts of the RAM area referred to as self RAM in self-programming or rewriting of
the data flash memory. For the sizes of the RAM areas used by the flash libraries, see "ROM, RAM
capacities" in 1.1 Features.
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively.
Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 20.5
RAM parity error detection function.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-1. Memory Map
FFFFF H
Special function registers (SFR)
256 bytes
FFF00 H
FFEFFH
General-purpose registers
32 bytes
FFEE0H
FFEDFH
Notes 1, 2, 4
RAM
1.5 KB
FF9 00 H
FF8FFH
Reserved
F 4 00 0 H
F3FFFH
Mirror
8 KB
F 2 00 0 H
F1FFFH
Reserved
F 1 80 0 H
F17FF H
Data flash memory
2 KB
F 1 00 0 H
F0FFFH
Reserved
F 0 8 00 H
F07FF H
Extended special function registers
(2nd SFR)
2 KB
F 0 00 0 H
EFFFFH
Reserved
0 4 00 0 H
03FFF H
Code flash memory
16 KB
0 0 00 0 H
CHAPTER 3 CPU ARCHITECTURE
0 3 F F F H
Program area
0 0 0 C E H
0 0 0 C DH
On-chip debug security
Note 3
ID setting area
10 bytes
0 0 0 C 4 H
0 0 0 C 3 H
Option byte area
0 0 0 C 0 H 4 bytes
0 0 0 B F H
CALLT table area
64 bytes
0 0 0 8 0 H
0 0 0 7 F H
Vector table area
128 bytes
0 0 0 0 0 H
Note 3
26