Renesas RL78/G1P Hardware User Manual page 269

RL78/G1P
A/D voltage comparator
Software
trigger mode
Hardware trigger
no-wait mode
Hardware trigger
wait mode
While in the software trigger mode or hardware trigger no-wait mode, the time from the rising of the ADCE
Notes 1.
bit to the falling of the ADCS bit must be following time or longer to stabilize the internal circuit.
[Stabilization wait status]
If a high-accuracy channel is selected as the analog input channel:
If a test mode setting (ADTES1 bit of ADTES register = 1) is selected: 0.5
If a standard channel is selected as the analog input channel:
If a temperature sensor output/internal reference voltage output are selected as the analog input channel:
(ADISS bit of ADS register = 1):
For the second and subsequent conversion in sequential conversion mode and for conversion of the
2.
channel specified by scan 1, 2, and 3 in scan mode, the A/D power supply stabilization wait time do not
occur after a hardware trigger is detected.
Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is
automatically switched to 1 when the hardware trigger signal is detected). However, it is possible
to clear the ADCS bit to 0 to specify the A/D conversion standby status.
2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is
not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion
stopped/conversion standby status).
4. To complete A/D conversion, specify at least the following time as the hardware trigger interval:
Hardware trigger no wait mode: 2 f
Hardware trigger wait mode: 2 f
wait time + A/D conversion time
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 9-4. Timing Chart When A/D Voltage Comparator Is Used
ADCE
Conversion
standby
ADCS Note 1
Conversion
standby
ADCS
Note 1
Set by writing 1 to
the ADCS bit.
A/D power
Conversion
standby
stabilization
wait time
ADCS
Hardware trigger
detection
A/D voltage comparator: enables operation
Conversion
operation
Cleared by writing 0 to the ADCS bit or automatically upon
Set by writing 1 to
completion of A/D conversion.
the ADCS bit.
Trigger Conversion
standby
operation
Hardware trigger
detection
Cleared by writing 0
to the ADCS bit.
supply
Note 2
Conversion
operation
Cleared by writing 0 to the ADCS bit or automatically upon
completion of A/D conversion.
clock + conversion start time + A/D conversion time
CLK
clock + Conversion start time + A/D power supply stabilization
CLK
CHAPTER 9 A/D CONVERTER
Conversion
Conversion
stopped
standby
Conversion
Conversion
stopped
standby
Conversion
Conversion
standby
stopped

0.5 s

s

2 s

2 s
250