12-Bit A/D Conversion Result Register (Adcr) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.3.5 12-bit A/D conversion result register (ADCR)

The higher 4 bits are fixed to 0. Each time A/D conversion ends, each time A/D conversion ends, the value of ADSAR
[11:0] is stored in the A/D conversion result register (note that whether to store this value is determined by the setting of
the ADRCK bit of the ADM2 register and by the settings of the ADUL and ADLL registers). The higher 4 bits of the
conversion result are stored in FFF1FH and the lower 8 bits are stored in the lower 4 bits of FFF1EH
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
If the A/D conversion result is outside the range specified by using the A/D conversion comparison function
Note
(the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 9-8), the
result is not stored.
Figure 9-9. Format of 12-bit A/D Conversion Result Register (ADCR)
Address: FFF1EH, FFF1FH
Symbol
ADCR
Cautions 1. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode
register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (bits 7 and
6 of the ADCR register).
2. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result
are read in order starting at bit 15.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: 0000H R
FFF1FH
CHAPTER 9 A/D CONVERTER
.
Note
FFF1EH
0 0 0 0 0 0
261