Renesas RL78/G1P Hardware User Manual page 162

16-bit single-chip microcontroller

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Table of Contents

Address: F0190H, F0191H (TMR00) to F0196H, F0197H (TMR03)

Operation clock (f

depending on the setting of the CCSmn bit.

The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3.

Operation clock (f

Valid edge of input signal input from the TImn pin

In channel 1, Valid edge of input signal selected by TIS0

Count clock (f

Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.

Cautions 1. Be sure to clear bits 13, 5, and 4 to "0".

2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for f

(by changing the value of the system clock control register (CKC)), even if the operating clock

specified by using the CKSmn0 and CKSmn1 bits (f

from the TImn pin is selected as the count clock (f

Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/4)

Selection of operation clock (f

Operation clock CKm0 set by timer clock select register m (TPSm)

Operation clock CKm2 set by timer clock select register m (TPSm)

Operation clock CKm1 set by timer clock select register m (TPSm)

Operation clock CKm3 set by timer clock select register m (TPSm)

) is used by the edge detector. A count clock (f

Selection of count clock (f

) specified by the CKSmn0 and CKSmn1 bits

) is used for the timer/counter, output controller, and interrupt controller.

After reset: 0000H

) and a sampling clock are generated

) of channel n

CHAPTER 6 TIMER ARRAY UNIT

) of channel n

) or the valid edge of the signal input