Renesas RL78/G1P Hardware User Manual page 600

16-bit single-chip microcontroller
Hide thumbs Also See for RL78/G1P:
Table of Contents

Advertisement

RL78/G1P
15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
The PR00L, PR00H, PR01L, PR10L, PR10H, and PR11L registers can be set by a 1-bit or 8-bit memory manipulation
instruction. If the PR00L and PR00H registers, and the PR10L and PR10H registers are combined to form 16-bit registers
PR00 and PR10, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 15-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L)
Address: FFFE8H
Symbol
<7>
PR00L
PPR05
Address: FFFECH
Symbol
<7>
PR10L
PPR15
Address: FFFE9H
Symbol
<7>
PR00H
SREPR00
TMPR001H
Address: FFFEDH
Symbol
<7>
PR10H
SREPR10
TMPR101H
Address: FFFEAH
Symbol
<7>
PR01L
TMPR003
Address: FFFEEH
Symbol
<7>
PR11L
TMPR103
XXPR1X
0
0
1
1
Caution Be sure to set bits that are not available to the initial value.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: FFH
R/W
<6>
<5>
PPR04
PPR03
After reset: FFH
R/W
<6>
<5>
PPR14
PPR13
After reset: FFH
R/W
<6>
<5>
SRPR00
STPR00
CSIPR000
After reset: FFH
R/W
<6>
<5>
SRPR10
STPR10
CSIPR100
After reset: FFH
R/W
<6>
<5>
TMPR002
TMPR001
After reset: FFH
R/W
<6>
<5>
TMPR102
TMPR101
XXPR0X
0
Specify level 0 (high priority level)
1
Specify level 1
0
Specify level 2
1
Specify level 3 (low priority level)
CHAPTER 15 INTERRUPT FUNCTIONS
<4>
<3>
PPR02
PPR01
<4>
<3>
PPR12
PPR11
<4>
<3>
DMAPR01
DMAPR00
<4>
<3>
DMAPR11
DMAPR10
<4>
<3>
TMPR000
IICAPR01
TMPR003H
<4>
<3>
TMPR100
IICAPR11
TMPR103H
Priority level selection
<2>
<1>
PPR00
LVIPR0
WDTIPR0
<2>
<1>
PPR10
LVIPR1
WDTIPR1
<2>
<1>
FLPR0
IICAPR00
ADPR0
<2>
<1>
FLPR1
IICAPR10
ADPR1
<2>
1
1
<2>
1
1
<0>
<0>
<0>
<0>
0
1
0
1
581

Advertisement

Table of Contents
loading

Table of Contents