Renesas RL78/G1P Hardware User Manual page 80

RL78/G1P
POP rp
<1>
Instruction code
OP-code
Stack addressing is specified <1>.
The contents of addresses SP and SP + 1 are stored in the
lower-order and higher-order bytes of the pair of registers
indicated by rp <2>, respectively.
The value of SP <3> is increased by two (if rp is the program
status word (PSW), the content of address SP + 1 is stored in
the PSW).
CALL
<1>
Instruction code
OP-code
Stack addressing is specified <1>. The value of the program
counter (PC) changes to indicate the address of the instruction
following the CALL instruction.
00H, the values of PC bits 19 to 16, 15 to 8, and 7 to 0 are stored
in addresses SP  1, SP  2, SP  3, and SP  4, respectively <2>.
The value of the SP <3> is decreased by 4.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-33. Example of POP
<2>
<1>
<2>
Figure 3-34. Example of CALL, CALLT
<1>
CHAPTER 3 CPU ARCHITECTURE
SP+2
SP
SP+1
SP
SP
rp
SP
SP1
SP2
SP3
<3> SP4
SP
<2>
PC
Stack
(SP+1)
area
(SP)
F0000H
Memory
Stack
00H
area
PC19PC16
PC15PC8
PC7PC0
F0000H
Memory
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