Higher 7 Bits Of The Serial Data Register Mn (Sdrmn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.5 Higher 7 bits of the serial data register mn (SDRmn)

The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 8 to 0 (lower 9 bits) of SDR00, SDR01 function as a transmit/receive buffer register, and bits 15 to 9 are used as a
register that sets the division ratio of the operation clock (f
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by
the higher 7 bits of the SDRmn register is used as the transfer clock.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (upper 7 bits) of SDR00 and SDR01 to
0000000B. The input clock f
The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 9 bits, and during transmission, the data to be transmitted to the
shift register is set to the lower 9 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 9 bits of the SDRmn register. When the SDRmn register is read during
operation, 0 is always read.
Reset signal generation clears the SDRmn register to 0000H.
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01)
Symbol 15 14
SDRmn
0 0
0 0
0 0
0 0
 
 
 
1 1
1 1
Cautions 1. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
2. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these bits are
written to, the higher seven bits are cleared to 0.)
Remarks 1. For the function of the lower 9 bits of the SDRmn register, see 11.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0), n: Channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
(slave transfer in CSI mode) from the SCKp pin is used as the transfer clock.
SCK
Figure 11-7. Format of Serial Data Register mn (SDRmn)
FFF11H (SDR00)
13 12 11 10
SDRmn[15:9]
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
   
   
   
1 1 1 1
1 1 1 1
CHAPTER 11 SERIAL ARRAY UNIT
, f ).
MCK SCK
After reset: 0000H
9 8 7 6
0
Transfer clock setting by dividing the operating clock (f
0 f /2, f
MCK
1
0
1



0
1
R/W
FFF10H (SDR00)
5 4 3 2
/2 (in CSI slave)
SCK
f /4
MCK
f /6
MCK
f /8
MCK



f /254
MCK
f /256
MCK
1 0
)
MCK
322