Renesas RL78/G1P Hardware User Manual page 643

RL78/G1P
18.4 Cautions for Power-on-reset Circuit
In a system where the supply voltage (V
(V , V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release
POR PDR
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 18-3. Example of Software Processing After Reset Release (1/2)
 If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage
Note 1
No
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
Remark m = 0, n = 0 to 3
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) fluctuates for a certain period in the vicinity of the POR detection voltage
DD
Reset
Initialization
processing <1>
Power-on-reset
Setting timer array unit
(to measure 50 ms)
Clearing WDT
50 ms has passed?
(TMIFmn = 1?)
Yes
Initialization
processing <2>
CHAPTER 18 POWER-ON-RESET CIRCUIT
; Check the reset source, etc.
; f = High-speed on-chip oscillator clock (4.04 MHz (MAX.))
CLK
Source: f = (4.04 MHz (MAX.))/2
MCK
where comparison value = 789: ≅ 50 ms
Timer starts (TSmn = 1).
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Note 2
7
,
624