Renesas RL78/G1P Hardware User Manual page 81

RL78/G1P
RET
<1>
Instruction code
OP-code
Stack addressing is specified <1>.
The contents of addresses SP, SP + 1, and SP + 2 are stored
in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
The value of SP <3> is increased by four.
Instruction code
OP-code
or
Interrupt
Stack addressing is specified <1>. In response to a BRK
instruction or acceptance of an interrupt, the value of the
program counter (PC) changes to indicate the address of
the next instruction.
The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to
0 are stored in addresses SP  1, SP  2, SP  3, and
SP  4, respectively <2>.
The value of the SP <3> is decreased by 4.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-35. Example of RET
SP
<1>
SP
PC
Figure 3-36. Example of Interrupt, BRK
PSW
SP
<1>
SP
PC
CHAPTER 3 CPU ARCHITECTURE
SP+4
SP+3
(SP+3)
SP+2
(SP+2)
SP+1 (SP+1)
<3>
SP
(SP)
<2>
Memory
<2>
SP1
PSW
SP2
PC19PC16
SP3
PC15PC8
<3> SP4
PC7PC0
<2>
Memory
Stack
area
F0000H
Stack
area
F0000H
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