Renesas RL78/G1P Hardware User Manual page 595

RL78/G1P
Interrupt
Type

Software BRK

Reset RESET
POR
LVD
WDT
TRAP
IAW
RPE
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 21 indicates the lowest priority.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 15-1.
3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1.
4. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 15-1. Interrupt Source List (2/2)
Interrupt Source
Execution of BRK instruction
RESET pin input
Power-on-reset
Note 3
Voltage detection
Overflow of watchdog timer
Execution of illegal instruction
Illegal-memory access
RAM parity error
CHAPTER 15 INTERRUPT FUNCTIONS
Note 4
Internal/ Vector
External Table
Address

0007EH

00000H
(C)

576