Renesas RL78/G1P Hardware User Manual page 241

RL78/G1P
(a) Timer mode register mn (TMRmn)
15 14
TMRmn
CKSmn1 CKSmn0
1/0 0
Operation clock (f
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0
MRm2: MASTERmn = 1
Note
TMRm0: Fixed to 0
m: Unit number (m = 0), n: Master channel number (n = 0, 2)
Remark
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-73. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
13 12 11 10
MASTER
CCSmn STSmn2 STSmn1
mn Note
0 0 1 0
Setting of MASTERmn bit (channel 2)
1: Master channel.
Count clock selection
0: Selects operation clock (f
) selection
MCK
0: Outputs 0 from TOmn.
0: Stops the TOmn output operation by counting operation.
0: Cleared to 0 when TOMmn = 0 (master channel output mode).
0: Sets master channel output mode.
9 8 7 6 5
STSmn0 CISmn1 CISmn0
0 0 0 0 0
Operation mode of channel n
000B: Interval timer
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
).
MCK
CHAPTER 6 TIMER ARRAY UNIT
4 3 2 1
MDmn3 MDmn2 MDmn1
0 0 0 0
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
0
MDmn0
1
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