Renesas RL78/G1P Hardware User Manual page 489

16-bit single-chip microcontroller
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RL78/G1P
12.3 Registers Controlling Serial Interface IICA
Serial interface IICA is controlled by the following eight registers.
• Peripheral enable register 0 (PER0)
• IICA control register n0 (IICCTLn0)
• IICA flag register n (IICFn)
• IICA status register n (IICSn)
• IICA control register n1 (IICCTLn1)
• IICA low-level width setting register n (IICWLn)
• IICA high-level width setting register n (IICWHn)
• Port mode register 6 (PM6)
• Port register 6 (P6)
Remark
n = 0, 1
12.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a
hardware that is not in use is stopped in order to reduce power consumption and noise.
When serial interface IICAn is to be used, be sure to set bits 6 and 4 (IICA1EN, IICA0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F0H
After reset: 00H
Symbol
7
PER0
0
IICAnEN
0
1
Cautions 1. When setting serial interface IICAn, be sure to set the IICAnEN bit to 1 first. If IICAnEN = 0,
writing to a control register of serial interface IICAn is ignored, and, even if the register is read,
only the default value is read (except for port mode register 6 (PM6) and port register 6 (P6)).
2. When using IICA of this product as a master, setting both the IICA0EN and IICA1EN bits to 1 is
prohibited because only one channel of IICA must be enabled to operate.
3. To make IICA of this product correspond to two slave addresses, both the IICA0EN and IICA1EN
bits must be set to 1.
4. Be sure to clear bits 1, 3, and 7 to "0".
Remark
n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-5. Format of Peripheral Enable Register 0 (PER0)
R/W
<6>
<5>
IICA1EN
ADCEN
Control of serial interface IICAn input clock supply
Stops input clock supply.
 SFR used by serial interface IICAn cannot be written.
 Serial interface IICAn is in the reset status.
Enables input clock supply.
 SFR used by serial interface IICAn can be read/written.
CHAPTER 12 SERIAL INTERFACE IICA
<4>
3
IICA0EN
0
<2>
1
SAU0EN
0
<0>
TAU0EN
470

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