Noise Filter Enable Register 0 (Nfen0) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.16 Noise filter enable register 0 (NFEN0)

The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin
to each channel.
Disable the noise filter of the pin used for CSI, by clearing the corresponding bit of this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
When the noise filter is enabled, CPU/peripheral hardware clock (f
When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (f
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Address: F0070H After reset: 00H
Symbol 7
NFEN0 0
SNFEN00
0
1
Set the SNFEN00 bit to 1 to use the R
Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Caution Be sure to clear bits 7 to 1 to "0".
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-20. Format of Noise Filter Enable Register 0 (NFEN0)
R/W
6 5
0 0
Use of noise filter of R
Noise filter OFF
Noise filter ON
D0 pin.
X
CHAPTER 11 SERIAL ARRAY UNIT
) is synchronized with 2-clock match detection.
CLK
4 3
0 0
D0 pin (RXD0/TOOLRXD/SDA00/SI00/P11)
X
).
MCK
2 1
0 0 SNFEN00
0
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