Renesas RL78/G1P Hardware User Manual page 270

RL78/G1P
(1) A/D conversion times for 12-bit A/D conversion when there is no power supply stabilization wait time
A/D Converter Mode Mode
Register 0 (ADM0)
FR2 FR1 FR0 LV0
0 0 0 0 Normal 1 f
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 1 Normal 2 f
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Note When using ANI16, setting this value is prohibited.
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 27.6.1 A/D converter characteristics.
2. Rewrite the FR2 to FR0 and LV0 bits to other than the same data while conversion is stopped (ADCS =
0, ADCE = 0).
3. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
4. In software trigger mode and hardware trigger no-wait mode, make settings that affect the
conversion time such that the following conditions are satisfied.
 f
must be in the range from 1 to 16 MHz.
AD
 When the setting of the ADISS bit of the ADS register is 1, selecting the temperature sensor or
internal reference voltage output, the following condition applies.
Setting LV0 to 0 is prohibited.
Only setting LV0 to 1 is permitted.
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 9-3. A/D Conversion Time Selection (1/4)
(for software trigger mode and hardware trigger no-wait mode)
Conversion Number of
Clock (f ) Conversion
AD
Clock
(Number of
Sampling
Clock)
/32 54 f
CLK AD
(number of
f /16 sampling
CLK
clock:
f /8
CLK
11 f )
AD
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1
CLK
/32 66 f
CLK AD
(number of
sampling
f /16
CLK
clock:
f /8
CLK
23 f )
AD
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1
CLK
Conversion
Time
f = 1 f
CLK CLK
MHz
1728/f Setting Setting
CLK
prohibited prohibited
864/f
CLK
432/f
CLK
324/f
CLK
270/f
CLK
216/f 54
CLK
108/f 27
CLK

54/f 54 s 13.5
Note
CLK
2112/f Setting Setting
CLK
prohibited prohibited
1056/f
CLK
528/f
CLK
396/f
CLK
330/f
CLK
66
264/f
CLK
132/f 33
CLK

66 s 16.5
66/f Note
CLK
CHAPTER 9 A/D CONVERTER
Selected Conversion Times
V = 2.7 to 3.6 V
DD
= 4 f = 8 f = 16
CLK CLK
MHz MHz MHz
Setting Setting
prohibited prohibited

54 s
Note
 
54 s 27 s
Note Note
 
40.5 s 20.25 s
Note
  s
33.75 s 16.875
Note
  
s 27 s 13.5 s
Note Note Note
  
s 13.5 s 6.75 s
Note Note Note
  
s 6.75 s 3.375 s
Note Note
Setting Setting
prohibited prohibited

66 s
 
66 s 33 s
Note
 
49.5 s 24.75 s
Note
 
41.25 s 20.625
Note
  
s 33 s 16.5 s
Note Note
  
s 16.5 s 8.25 s
Note Note
  
s 8.25 s 4.125 s
Note Note
f = 32
CLK
MHz

54 s
Note

27 s
Note

13.5 s
Note

10.125 s
Note Note

8.4375 s
Note Note

6.75 s
Note

3.375 s
Note
Setting
Note
prohibited

66 s

33 s

16.5 s

12.375 s

s 10.3125 s

8.25 s

4.125 s
Setting
prohibited
)
CONV
251