Port Registers (Pxx) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

4.3.2 Port registers (Pxx)

These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
Note
read .
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note If P20 to P27 are set up as analog inputs of the A/D converter, when a port is read while in the input mode, 0 is
always returned, not the pin level.
Symbol 7 6
Note 3
P1 P17 P16
Note 3
P2 P27 P26
P3 0 0
P4 0 0
P6 0 0
P12 0 0
P13 P137 0
Pmn
0 Output 0
1 Output 1
Notes 1. P121, P122, and P137 are read-only.
2. P137: Undefined
3. These are not provided in 24-pin products.
Remark m = 1 to 4, 6, 12, 13; n = 0 to 7
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 4-17. Format of Port Register
5 4 3
Note 3
P15 P14 P13
Note 3 Note 3
P25 P24 P23
Note 3 Note 3
P35 P34 P33
0 0 0
0 0 0
0 0 0
0 0 0
Output data control (in output mode)
CHAPTER 4 PORT FUNCTIONS
2 1 0
Note 3
P12 P11 P10
P22 P21 P20
P32 P31 P30
0 0 P40
0 P61 P60
P122 P121 0
0 0 0
Input data read (in input mode)
Input low level
Input high level
Address After reset
FFF01H 00H (output latch) R/W
FFF02H 00H (output latch) R/W
FFF03H 00H (output latch) R/W
FFF04H 00H (output latch) R/W
FFF06H 00H (output latch) R/W
FFF0CH Undefined
FFF0DH Note 2
R/W
Note 1
R/W
Note 1
R/W
86