Renesas RL78/G1P Hardware User Manual page 648

RL78/G1P
19.3.2 Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H
Figure 19-3. Format of Voltage Detection Level Select Register (LVIS)
Address: FFFAAH
Symbol <7>
LVIS LVIMD
Note 2
LVIMD
0
1
Note 2
LVILV
0
1
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follows.
 When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
 When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
 When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
2. Writing "0" can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset
mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically
when reset or interrupt is generated.
Cautions 1. Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register)
to 1.
2. Specify the LVD operation mode and detection voltage (V
byte (000C1H). Table 19-1 shows the option byte (000C1H) settings. For details about the
option byte, see CHAPTER 22 OPTION BYTE.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Note 1
After reset: 00H/01H/81H
6 5
0 0
Interrupt mode
Reset mode
High-voltage detection level (V
Low-voltage detection level (V
CHAPTER 19 VOLTAGE DETECTOR
Note 1
.
R/W
4 3
0 0
Operation mode of voltage detection
LVD detection level
)
LVDH
or V )
LVDL LVDL
2 1
0 0 LVILV
, V , V ) by using the option
LVDH LVDL LVD
<0>
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