Renesas RL78/G1P Hardware User Manual page 139

RL78/G1P
Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/3)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Status Transition
(A)  (B)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A)  (B)  (C)
(X1 clock: 1 MHz  f  10 MHz)
X
(A)  (B)  (C)
 20 MHz)
(X1 clock: 10 MHz < f
X
(A)  (B)  (C)
(external main clock)
The clock operation mode control register (CMC) can be written only once by an 8-bit memory
Notes 1.
manipulation instruction after reset release.
Set the oscillation stabilization time as follows.
2.
 Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time 
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS).
Remarks 1. ×: don't care
2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
SFR registers do not have to be set (default status after reset release).
CMC Register
Note 1
EXCLK OSCSEL AMPH
0 1 0
0 1 1

1 1
CHAPTER 5 CLOCK GENERATOR
SFR Register Setting
OSTS CSC OSTC Register
Register Register
MSTOP
0 Must be
Note 2
checked
0 Must be
Note 2
checked
0 Must not be
Note 2
checked
CKC
Register
MCM0
1
1
1
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