Renesas RL78/G1P Hardware User Manual page 727

RL78/G1P
Instruction Mnemonic
Group
8-bit SUBC A, #byte
operation
saddr, #byte
A, r
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
AND A, #byte
saddr, #byte
A, r
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 26-5. Operation List (8/18)
Operands Bytes
Note 1 Note 2
2
3
Note 3
2
2
3
4
2
1
2
2
3
2
3
2
3
2
3
Note 3
2
2
3
4
2
1
2
2
3
2
3
2
3
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the program memory area is accessed.
CLK
Clocks
 A, CY  A – byte – CY
1
 (saddr), CY  (saddr) – byte – CY
2
 A, CY  A – r – CY
1
 r, CY  r – A – CY
1
A, CY  A – (addr16) – CY
1 4
A, CY  A – (ES, addr16) – CY
2 5
 A, CY  A – (saddr) – CY
1
A, CY  A – (HL) – CY
1 4
A,CY  A – (ES, HL) – CY
2 5
A, CY  A – (HL+byte) – CY
1 4
A,CY  A – ((ES, HL)+byte) – CY
2 5
A, CY  A – (HL+B) – CY
1 4
A,CY  A – ((ES, HL)+B) – CY
2 5
A, CY  A – (HL+C) – CY
1 4
A, CY  A – ((ES:HL)+C) – CY
2 5
 A  A  byte
1
 (saddr)  (saddr)  byte
2
 A  A  r
1
 R  r  A
1
A  A  (addr16)
1 4
A  A  (ES:addr16)
2 5
 A  A  (saddr)
1
A  A  (HL)
1 4
A  A  (ES:HL)
2 5
A  A  (HL+byte)
1 4
A  A  ((ES:HL)+byte)
2 5
A  A  (HL+B)
1 4
A  A  ((ES:HL)+B)
2 5
A  A  (HL+C)
1 4
A  A  ((ES:HL)+C)
2 5
CHAPTER 26 INSTRUCTION SET
Operation Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
708